Lattice Semiconductor has announced the Lattice CrossLinkU™-NX FPGA family, the industry’s first FPGAs with integrated USB device functionality in their class. It extends small, low-power FPGA portfolio with first-in-class FPGA featuring hardened USB for AI & embedded vision applications.
CrossLinkU-NX FPGAs helps to accelerate USB-equipped system designs and simplify thermal management through a combination of a hardened USB controller and physical layer (PHY), a unique low power standby mode, and a complete set of reference designs. Extending Lattice’s embedded vision sensor bridg-ing leadership with USB host interfaces, CrossLinkU-NX FPGAs are designed to meet growing customer needs to simplify USB-based design for applications across the Computing, Industrial, Automotive, and Consumer markets.
“Reducing power consumption, the total cost of ownership, and design footprint are critical for expanding the potential of AI and vision applications,” said Dan Mansur, Vice President, Product Marketing, Lattice Semiconductor. “Lattice CrossLinkU-NX FPGAs are optimized to address these demands by integrating our low power, small form factor leadership with the popular USB connectivity interface to help designers extend battery life and simplify system design.”
Built on the award-winning Lattice Nexus™ platform, key features and performance highlights of the new low power Lattice CrossLinkU-NX FPGAs include:
Vision Processing FPGAs with USB
- Featuring hardened USB 2.0 up to 480 Mbps and USB 3.2 up to 5 Gbps
- Reducing total cost of ownership and area needed for discrete PHY components
- Reducing FPGA fabric resources required for USB device controller
Low Power Standby Mode with Always-On (AON)
- Extending battery life and simplifying system thermal management
- Optimising power consumption in a typical embedded vision application
Complete Set of Reference Designs
- Offering a Lattice Propel™ template, host driver, and example host utilities for USB to I/O bridging and MIPI CSI-2 to USB bridging applications to accelerate USB device implementation on the FPGA